AMIS30532C5321G Datasheet, PDF (21/29 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30532
SPI INTERFACE
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with
AMIS−30532. The implemented SPI block is designed to
interface directly with numerous micro−controllers from
several manufacturers. AMIS−30532 acts always as a Slave
and can’t initiate any transmission. The operation of the
device is configured and controlled by means of SPI
registers which are observable for read and/or write from the
Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
DO signal is the output from the Slave (AMIS−30532), and
DI signal is the output from the Master. A chip select line
(CS) allows individual selection of a Slave SPI device in a
multiple−slave system. The CS line is active low. If
AMIS−30532 is not selected, DO is pulled up with the
external pull up resistor. Since AMIS−30532 operates as a
Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks
data out on the falling edge and samples data in on rising
edge of clock. The Master SPI port must be configured in
MODE 0 too, to match this operation. The SPI clock idles
low between the transferred bytes.
The diagram below is both a Master and a Slave timing
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
# CLK cycle
CS
1
2
3
4
5
6
7
8
CLK
DI
MSB
6
5
4
3
2
1 LSB ^{ÎÎÎÎÎÎÎÎ}
DO
MSB
6
5
4
3
2
1 LSB ^{ÎÎÎÎÎÎÎÎÎ}
Figure 18. Timing Diagram of an SPI Transfer
NOTE: At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the addressed internal SPI
register. The internal SPI registers are updated at the first rising edge of the AMIS−30532 system clock when CS = High
Transfer Packet
Serial data transfer is assumed to follow MSB first rule.
The transfer packet contains one or more 8−bit characters
(bytes).
BYTE 1
Command and SPI Register Address
BYTE 2
Data
MSB
LSB
MSB
LSB
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Command
SPI Register Address
Figure 19. SPI Transfer Packet
Byte 1 contains the Command and the SPI Register
Address and indicates to AMIS−30532 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from AMIS−30532 in a READ operation.
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