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AMIS30532C5321G Datasheet, PDF (19/29 Pages) ON Semiconductor – Micro-Stepping Motor Driver | |||
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AMISâ30532
voltages. If supply voltage is too low or external components
are not properly connected to guarantee RDS(on) of the
drivers, then the bit <CPFAIL> is set (Table 16). Also after
POR the charge pump voltage will need some time to exceed
the required threshold. During that time <CPFAIL> will be
set to â1â.
Error Output
This is a digital output to flag a problem to the external
microcontroller. The signal on this output is active low and
the logic combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR
<OVCYij> OR <OPENi> OR <CPFAIL>
Logic Supply Regulator
AMISâ30532 has an onâchip 5 V lowâdrop regulator
with external capacitor to supply the digital part of the chip,
VBB
some lowâvoltage analog blocks and external circuitry. The
voltage is derived from an internal bandgap reference. To
calculate the available driveâcurrent for external circuitry,
the specified Iload should be reduced with the consumption
of internal circuitry (unloaded outputs) and the loads
connected to logic outputs. See Table 5 DC Parameters.
PowerâOn Reset (POR) Function
The open drain output pin POR/WD provides an âactive
lowâ reset for external purposes. At powerâup of
AMISâ30532, this pin will be kept low for some time to reset
for example an external microcontroller. A small analog
filter avoids resetting due to spikes or noise on the VDD
supply.
VDD
tPU
t
tPD
VDDH
VDDL
t
< tRF
POR/WD pin
tPOR
tRF
Figure 16. PowerâonâReset Timing Diagram
Watchdog Function
The watchdog function is enabled/disabled through
<WDEN> bit (Table 13: SPI CONTROL REGISTERS (ALL
SPI control registers have Read/Write Access and default to
â0â after powerâon or hard reset.)). Once this bit has been set
to â1â (watchdog enable), the microcontroller needs to
reâwrite this bit to clear an internal timer before the
watchdog timeout interval expires. In case the timer is
activated and WDEN is acknowledged too early (before
tWDPR) or not within the interval (after tWDTO), then a reset
of the microcontroller will occur through POR/WD pin. In
addition, a warm/cold boot bit <WD> is available (see
Tables 16 and 17) for further processing when the external
microcontroller is alive again.
CLR Pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMISâ30532, the input
CLR needs to be pulled to logic 1 during minimum time
given by tCLR. (Table 6 AC Parameters). This reset function
clears all internal registers without the need of a
powerâcycle, except in sleep mode. The operation of all
analog circuits is depending on the reset state of the digital,
charge pump remains active. Logic 0 on CLR pin resumes
normal operation again.
The voltage regulator remains functional during and after
the reset and the POR/WD pin is not activated. Watchdog
function is reset completely.
Sleep Mode
The bit <SLP> in SPI Control Register 2 (See Table 12)
is provided to enter a soâcalled âsleep modeâ. This mode
allows reduction of currentâconsumption when the motor is
not in operation. The effect of sleep mode is as follows:
⢠The drivers are put in HiZ
⢠All analog circuits are disabled and in lowâpower mode
⢠All internal registers are maintaining their logic content
⢠NXT and DIR inputs are forbidden
⢠SPI communication remains possible (slight current
increase during SPI communication)
⢠Reset of chip is possible through CLR pin
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