English
Language : 

MTB50P03HDL_14 Datasheet, PDF (2/9 Pages) ON Semiconductor – P-Channel Power MOSFET
MTB50P03HDL, MVB50P03HDLT4G
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 3)
V(BR)DSS
30
−
−
26
Vdc
−
−
mV/°C
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate−Body Leakage Current
(VGS = ±15 Vdc, VDS = 0 Vdc)
IDSS
mAdc
−
−
1.0
−
−
10
IGSS
nAdc
−
−
100
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 3.0) (Note 3)
VGS(th)
Vdc
1.0
1.5
2.0
−
4.0
−
mV/°C
Static Drain−Source On−Resistance
(VGS = 5.0 Vdc, ID = 25 Adc)
Drain−Source On−Voltage (VGS = 5.0 Vdc)
(ID = 50 Adc)
(ID = 25 Adc, TJ =125°C)
Forward Transconductance
(VDS = 5.0 Vdc, ID = 25 Adc)
(Cpk ≥ 3.0) (Note 3)
RDS(on)
mW
−
20.9
25
VDS(on)
Vdc
−
0.83
1.5
−
−
1.3
gFS
mhos
15
20
−
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD= 15 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc, RG = 2.3 W)
Fall Time
Gate Charge (See Figure 8)
(VDS = 24 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
−
3500 4900
pF
−
1550 2170
−
550
770
−
22
30
ns
−
340
466
−
90
117
−
218
300
−
74
100
nC
−
13.6
−
−
44.8
−
−
35
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 50 Adc, VGS = 0 Vdc)
VSD
(IS = 50 Adc, VGS = 0 Vdc, TJ = 125°C)
Vdc
−
2.39
3.0
−
1.84
−
Reverse Recovery Time
(See Figure 15)
Reverse Recovery Stored Charge
(IS = 50 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
trr
ta
tb
QRR
−
106
−
ns
−
58
−
−
48
−
−
0.246
−
mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
−
3.5
−
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
3. Reflects typical values.
Max limit − Typ
Cpk =
3 x SIGMA
LS
−
7.5
−
nH
http://onsemi.com
2