NOIL2SM1300A Datasheet, PDF (14/44 Pages) ON Semiconductor – LUPA1300-2: High Speed CMOS Image Sensor

NOIL2SM1300A
Table 9. INTERNAL REGISTERS
Block Register Name Address [6..0]
tint_ds_timer1
81
tint_ds_timer2
82
tint_ts_timer1
83
tint_ts_timer2
84
tint_black_timer
85
rot_timer
86
fot_timer
87
fot_timer
88
prechpix_timer
89
prechpix_timer
90
prechcol_timer
91
rowselect_timer
92
sample_timer
93
sample_timer
94
vmem_timer
95
vmem_timer
96
delayed_rdt_tim-
97
er
delayed_rdt_tim-
98
er
Fix29
99
Fix30
100
Fix31
101
Fix32
102
Fix33
103
Fix34
104
Field
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[7:0]
[0]
[0]
[0]
[0]
[0]
[0]
Reset Value
Description
0x40
Length of DS integration time (granularity selectable)
0x00
Length of DS integration time (granularity selectable)
0x0C
Length of TS integration time (granularity selectable)
0x00
Length of TS integration time (granularity selectable)
0x06
Reserved, fixed value
0x09
Length of ROT (granularity clock cycles)
0x3B
Length of FOT (granularity clock cycles)
0x01
Length of FOT (granularity clock cycles)
0x7C
Length of pixel precharge (granularity clock cycles)
0x00
Length of pixel precharge (granularity clock cycles)
0x03
Length of column precharge (granularity clock cycles)
0x06
Length of rowselect (granularity clock cycles)
0xF8
Length of pixel_sample (granularity clock cycles)
0x00
Length of pixel_sample (granularity clock cycles)
0x10
Length of pixel_vmem (granularity clock cycles)
0x01
Length of pixel_vmem (granularity clock cycles)
0
Readout delay for testing purposes (granularity selectable)
0
Readout delay for testing purposes (granularity selectable)
0
Reserved, fixed value
0
Reserved, fixed value
0
Reserved, fixed value
0
Reserved, fixed value
0
Reserved, fixed value
0
Reserved, fixed value
Detailed Description of Internal Registers
The registers must be changed only during idle mode, that
is, when seqmode1[0] is ‘0’. Uploaded registers have an
immediate effect on how the frame is read out. Parameters
uploaded during readout may have an undesired effect on the
data coming out of the images.
MBS Block
The register block contains registers for sensor testing and
debugging. All registers in this block must remain
unchanged after startup.
LVDS Clock Divider Block
This block controls division of the input clock for the
LVDS transmitters or receivers. This block also enables
shutting down one or all LVDS channels. For normal
operation, this register block must remain untouched after
startup.
AFE Block
This register block contains registers to shut down ADC
channels or the complete AFE block. This block also
contains the register for setting the PGA gain:
AFE_mode[5:3]. Refer to Absolute Maximum Ratings on
page 3 for more details on the PGA settings.
Biasing Block
This block contains several registers for setting biasing
currents for the sensor. Default values after startup must
remain unchanged for normal operation of the sensor.
Image Core Block
The registers in this block have an impact on the pixel
array itself. Default settings after startup must remain
unchanged for normal operation of the image sensor.
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