MUN5311DW1T1G_09 Datasheet, PDF (1/34 Pages) ON Semiconductor – Dual Bias Resistor Transistors

MUN5311DW1T1G Series
Preferred Devices
Dual Bias Resistor
Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The Bias Resistor Transistor (BRT) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the
MUN5311DW1T1G series, two complementary BRT devices are
housed in the SOT−363 package which is ideal for low power surface
mount applications where board space is at a premium.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Available in 8 mm, 7 inch/3000 Unit Tape and Reel
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (T_A = 25°C unless otherwise noted, common for Q₁
and Q₂, − minus sign for Q₁ (PNP) omitted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
V_CBO
50
Collector-Emitter Voltage
V_CEO
50
Collector Current
I_C
100
THERMAL CHARACTERISTICS
Vdc
Vdc
mAdc
Characteristic
(One Junction Heated)
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
P_D
187 (Note 1)
mW
256 (Note 2)
1.5 (Note 1) mW/°C
2.0 (Note 2)
Thermal Resistance −
Junction-to-Ambient
R_qJA
670 (Note 1)
490 (Note 2)
°C/W
Characteristic
(Both Junctions Heated)
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
P_D
250 (Note 1)
mW
385 (Note 2)
2.0 (Note 1) mW/°C
3.0 (Note 2)
Thermal Resistance −
Junction-to-Ambient
R_qJA
493 (Note 1)
325 (Note 2)
°C/W
Thermal Resistance −
Junction-to-Lead
R_qJL
188 (Note 1)
208 (Note 2)
°C/W
Junction and Storage Temperature T_J, T_stg −55 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
© Semiconductor Components Industries, LLC, 2009
1
October, 2009 − Rev. 12
http://onsemi.com
(3)
(2)
(1)
R₁
R₂
Q₁
Q₂
R₂
R₁
(4)
(5)
(6)
6
1
SOT−363
CASE 419B
STYLE 1
MARKING DIAGRAM
6
xx M G
G
1
xx
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING AND DEVICE MARKING
INFORMATION
See detailed ordering, shipping, and specific marking
information in the table on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MUN5311DW1T1/D