MC74AC74_15 Datasheet, PDF (1/10 Pages) ON Semiconductor – Dual D-Type Positive Edge-Triggered Flip-Flop

MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual D−type flip−flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
Asynchronous Inputs:
LOW input to S_D (Set) sets Q to HIGH level
LOW input to C_D (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C_D and S_D makes both Q and Q HIGH
Features
• Outputs Source/Sink 24 mA
• ′ACT74 Has TTL Compatible Inputs
• These are Pb−Free Devices
V_CC C_D2 D₂ CP₂ S_D2 Q₂ Q₂
14 13 12 11 10 9 8
D₁ ^CD1 Q₁
CP_{1 SD1} Q₁
CP₂ ^SD2 Q₂
D_{2 CD2} Q₂
1234567
C_D1 D₁ CP₁ S_D1 Q₁ Q₁ GND
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
FUNCTION
D₁, D₂
CP₁, CP₂
C_D1, C_D2
S_D1, S_D2
Q₁, Q₁, Q₂,
Q₂
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
www.onsemi.com
14
1
MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
xxx74G
AWLYWW
1
1
14
TSSOP−14
DT SUFFIX
CASE 948G
14
xxx
74
ALYWG
G
1
xxx
= AC or ACT
A
= Assembly Location
WL or L = Wafer Lot
Y
= Year
WW or W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
January, 2015 − Rev. 8
Publication Order Number:
MC74AC74/D