CM2009-05CP Datasheet, PDF (1/8 Pages) ON Semiconductor – VGA or DVI-I Port Companion Circuit

VGA or DVI-I Port Companion Circuit
CM2009-05CP
Advance Information
Features
• Includes ESD protection, level-shifting, buffering
and sync impedance matching
• VESA VSIS Version 1 Revision 2 compatible
interface
• Supports both source and sink devices
• Supports optional NAVI signaling requirements
• Seven channels of ESD protection for all VGA
port connector pins meeting IEC-61000-4-2 Level
4 ESD requirements (±8kV contact discharge)
• Very low loading capacitance from ESD
protection diodes on VIDEO lines, 3pF maximum
• Schmitt-triggered input buffers for HSYNC and
VSYNC lines
• Bi-directional level shifting N-channel FETs
provided for DDC_CLK & DDC_DATA channels
• Backdrive protection on all lines
• RoHS-compliant, lead-free finishing in a 14-
bump, 5x4x5, 0.4mm Chip Scale Package (CSP)
Applications
•
Monitors
•
Video graphics controllers embedded in PCs
•
Graphics adapter cards
•
Set-top boxes
Product Description
The CM2009-05CP connects between the VGA or
DVI-I port connector and the internal analog or digital
flat panel controller logic. It can also be used for
source devices such as a set-top box. The CM2009-
05CP incorporates ESD protection for all signals,
level shifting for the DDC signals and buffering for the
SYNC signals. ESD protection for the video, DDC
and SYNC lines is implemented with low-capacitance
current steering diodes.
All connector interface pins are designed to safely
handle the high current spikes specified by IEC-
61000-4-2 Level 4 (±8kV contact discharge). The
ESD protection for the DDC, SYNC and VIDEO
signal pins is designed to prevent "back current"
when the device is powered down while connected to
a video source or a video sink that is powered up.
Positive supply rails are provided for the VIDEO /
SYNC signals and DDC signals to facilitate
interfacing with low voltage video controller ICs and
microcontrollers to provide design flexibility in multi-
supply-voltage environments.
Two Schmitt-triggered non-inverting buffers redrive
and condition the HSYNC and VSYNC signals from
the video connector (SYNC1, SYNC2). These buffers
accept VESA VSIS compliant TTL input signals and
convert them to CMOS output levels that swing
between ground and V_CC.
Two N-channel MOSFETs provide the level shifting
function required when the DDC controller or EDID
EEPROM is operated at a lower supply voltage than
the monitor. The gate terminals for these MOSFETS
should be connected to the supply rail (typically 3.3V,
2.5V etc.) that supplies power to the transceivers of
the DDC controller.
©2010 SCILLC. All rights reserved.
April 2010 Rev. P2
Publication Order Number:
CM2009-05CP/D