MKL82Z128VLK7 Datasheet, PDF (95/133 Pages) NXP Semiconductors – 72 MHz ARM® Cortex®-M0+ with 128 KB Flash and 96 KB SRAM

Electrical characteristics
5.4.2.4.2 32 kHz oscillator frequency specifications
Table 59. 32 kHz oscillator frequency specifications
Symbol Description
f_{osc_lo}
t_start
f_{ec_extal32}
v_{ec_extal32}
Oscillator crystal
Crystal start-up time
Externally provided input clock frequency
Externally provided input clock amplitude
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
—
1000
—
ms
—
32.768
—
kHz
700
—
V_BAT
mV
Notes
1
2
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and V_IH and V_IL specifications do not apply. The voltage of the
applied clock must be within the range of V_SS to V_BAT.
5.4.3 Memories and memory interfaces
5.4.3.1 QuadSPI AC specifications
• All data is based on a negative edge data launch from the device and a positive
edge data capture, as shown in the timing diagrams in this section.
• Measurements are with a load of 15pf (1.8V) and 35pf (3V) on output pins. Input
slew: 1ns
• Timings assume a setting of 0x0000_000x for QuadSPI _SMPR register (see the
reference manual for details).
The following table lists the QuadSPI delay chain read/write settings. Please see the
device reference manual for register and bit descriptions.
Table 60. QuadSPI delay chain read/write settings
Mode
SDR
DDR
Hyperflash
QuadSPI_MCR[DQ
S_EN]
Yes
QuadSPI registers
QuadSPI_SOCCR[ QuadSPI_MCR[SC
SOCCFG]
LKCFG]
3Fh
5
Yes
3Fh
1
RDS driven from
0h
No
Flash
QuadSPI_FLSHC
R[TDH]
No
2
2
Notes
Delay of 63
buffer and 64
mux
Delay of 63
buffer and 64
mux
Delay of 1 mux
SDR mode
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
95
NXP Semiconductors