MKL82Z128VLK7 Datasheet, PDF (121/133 Pages) NXP Semiconductors – 72 MHz ARM® Cortex®-M0+ with 128 KB Flash and 96 KB SRAM

Electrical characteristics
Num
DS9
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Table 87. Slave mode DSPI timing (full voltage range)
Description
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Min.
1.71
—
8 x t_BUS
(t_SCK/2) - 4
—
0
2.6
7.0
—
—
Max.
3.6
7.5
—
(t_SCK/2) + 4
23.1
—
—
—
13.0
13.0
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
DS11
DS16
Last data
Last data
Figure 43. DSPI classic SPI timing — slave mode
5.4.7.5 Inter-Integrated Circuit Interface (I2C) timing
Table 88. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency
f_SCL
0
Hold time (repeated) START condition. t_HD; STA
4
After this period, the first clock pulse is
generated.
100
0
400¹
kHz
—
0.6
—
µs
LOW period of the SCL clock
t_LOW
4.7
—
1.25
—
µs
HIGH period of the SCL clock
t_HIGH
4
—
0.6
—
µs
Set-up time for a repeated START
t_SU; STA
4.7
—
0.6
—
µs
condition
Data hold time for I²C bus devices
t_HD; DAT
0²
3.45³
0⁴
0.9²
µs
Table continues on the next page...
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
121
NXP Semiconductors