MKL82Z128VLK7 Datasheet, PDF (8/133 Pages) NXP Semiconductors – 72 MHz ARM® Cortex®-M0+ with 128 KB Flash and 96 KB SRAM

Overview
Table 2. AWIC Partial Stop, Stop and VLPS wake-up sources
Wake-up source
Available system resets
Low-voltage detect
Low-voltage warning
Pin interrupts
ADC0
CMPx
I2Cx
LPUARTx
USB FS/LS Controller
FlexIO0
LPTMR
RTC
TPM
TSI0
NMI
Description
RESET_b pin and WDOG when LPO is its clock source, and Debug
Power mode controller
Power mode controller
Port control module - any enabled pin interrupt is capable of waking the system
The ADC is functional when using internal clock source
Since no system clocks are available, functionality is limited, trigger mode provides wakeup
functionality with periodic sampling
Address match wakeup
Functional when using clock source which is active in Stop and VLPS modes
Wakeup
Functional when using clock source which is active in Stop and VLPS modes
Functional when using clock source which is active in Stop, VLPS and LLS/VLLS modes
Functional in Stop/VLPS modes
Functional when using clock source which is active in Stop and VLPS modes
Wakeup
Non-maskable interrupt
2.1.4 Memory
This device has the following features:
• 96 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait
states.
• The non-volatile memory is divided into two arrays
• 128 KB of embedded program memory
• 32 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI
interfaces)
The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program flash
is 1 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
The security circuitry prevents unauthorized access to RAM or flash contents from
debug port.
• System register file
8
NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 3, 08/2016