74AUP2G38 Datasheet, PDF (9/17 Pages) NXP Semiconductors – Low-power dual 2-input NAND gate (open-drain)

NXP Semiconductors
74AUP2G38
Low-power dual 2-input NAND gate; open drain
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
Conditions
25 °C
Min Typ^[1] Max
C_L = 5 pF, 10 pF, 15 pF and 30 pF
C_PD
power dissipation f = 1 MHz; V_I = GND to V_CC ^[3]
capacitance
V_CC = 0.8 V
-
V_CC = 1.1 V to 1.3 V
-
V_CC = 1.4 V to 1.6 V
-
V_CC = 1.65 V to 1.95 V
-
V_CC = 2.3 V to 2.7 V
-
V_CC = 3.0 V to 3.6 V
-
0.6 -
0.7 -
0.8 -
0.9 -
1.1 -
1.4 -
−40 °C to +125 °C
Unit
Min Max
Max
(85 °C) (125 °C)
-
-
-
pF
-
-
-
pF
-
-
-
pF
-
-
-
pF
-
-
-
pF
-
-
-
pF
[1] All typical values are measured at nominal V_CC.
[2] t_pd is the same as t_PZL and t_PLZ.
[3] C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N where:
f_i = input frequency in MHz;
V_CC = supply voltage in V;
N = number of inputs switching.
12. Waveforms
V_I
nA, nB input
GND
V_CC
nY output
V_OL
V_M
t _PLZ
V_X
t _PZL
V_M
mnb132
Fig 8.
Measurement points are given in Table 9.
Logic level V_OL is a typical output voltage level that occurs with the output load.
The data input (nA, nB) to output (nY) propagation delays
Table 9. Measurement points
Supply voltage
V_CC
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
V_M
0.5V_CC
0.5V_CC
0.5V_CC
Output
V_M
0.5V_CC
0.5V_CC
0.5V_CC
V_X
V_OL + 0.1 V
V_OL + 0.15 V
V_OL + 0.3 V
74AUP2G38_4
Product data sheet
Rev. 04 — 8 October 2009
© NXP B.V. 2009. All rights reserved.
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