74AUP2G38 Datasheet, PDF (2/17 Pages) NXP Semiconductors – Low-power dual 2-input NAND gate (open-drain)

NXP Semiconductors
74AUP2G38
Low-power dual 2-input NAND gate; open drain
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP2G38DC −40 °C to +125 °C VSSOP8
74AUP2G38GT −40 °C to +125 °C XSON8
74AUP2G38GD −40 °C to +125 °C XSON8U
74AUP2G38GM −40 °C to +125 °C XQFN8U
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2. Marking codes
Type number
74AUP2G38DC
74AUP2G38GT
74AUP2G38GD
74AUP2G38GM
Marking code^[1]
a38
a38
a38
a38
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1A
1Y
1B
2A
2Y
2B
001aah753
Fig 1. Logic symbol
&
&
001aah754
Fig 2. IEC logic symbol
Y
A
B
GND
mnb131
Fig 3. Logic diagram (one gate)
74AUP2G38_4
Product data sheet
Rev. 04 — 8 October 2009
© NXP B.V. 2009. All rights reserved.
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