ISP1563 Datasheet, PDF (89/103 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

NXP Semiconductors
ISP1563
HS USB PCI host controller
Table 133. Dynamic characteristics: low-speed source electrical characteristics
V_{DDA_AUX} = 3.0 V to 3.6 V; T_amb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at V_{DDA_AUX} = 3.3 V; T_amb = +25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Driver characteristics
t_LR
t_LF
t_LRFM
transition time: rise time
transition time: fall time
rise and fall time matching
75
-
75
-
90
-
Max
Unit
300
ns
300
ns
125
%
16.1 Timing
Table 134. PCI clock and I/O timing
V_{DDA_AUX} = 3.0 V to 3.6 V; T_amb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at V_{DDA_AUX} = 3.3 V; T_amb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PCI clock timing; see Figure 7
T_cyc(PCICLK)
PCICLK cycle time
t_HIGH(PCICLK)
PCICLK HIGH time
t_LOW(PCICLK)
PCICLK LOW time
SR_PCICLK
PCICLK slew rate
SR_RST#
RST# slew rate
PCI input timing; see Figure 8
30
-
11
-
11
-
1
-
50
-
32
ns
-
ns
-
ns
4
V/ns
-
mV/ns
t_su(PCICLK)bs
t_{su(PCICLK)ptp}
set-up time to PCICLK (bus signal)
set-up time to PCICLK
(point-to-point)
7
-
-
ns
[1] ₁₀
-
-
ns
t_h(PCICLK)
input hold time from PCICLK
PCI output timing; see Figure 9
0
-
-
ns
t_{val(PCICLK)bs}
PCICLK to signal valid delay (bus
signal)
2
-
11
ns
t_{val(PCICLK)ptp}
PCICLK to signal valid delay
(point-to-point)
[1] ₂
-
12
ns
t_dZ(act)
float to active delay
t_d(act)Z
active to float delay
PCI reset timing
2
-
-
-
-
ns
28
ns
t_rst
t_rst-clk
reset active time after power stable
reset active time after CLK stable
1
-
-
ms
100
-
-
µs
[1] REQ# and GNT# are point-to-point signals. GNT# has a setup of 10 ns; REQ# has a set up of 12 ns. All others are bus signals.
ISP1563_3
Product data sheet
Rev. 03 — 18 November 2008
© NXP B.V. 2008. All rights reserved.
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