ISP1563 Datasheet, PDF (74/103 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

NXP Semiconductors
ISP1563
HS USB PCI host controller
11.4.3 USBINTR register
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in the USBSTS to allow the software to poll for events. The USBSTS
register bit allocation is given in Table 107.
Table 107. USBINTR - USB Interrupt Enable register bit allocation
Address: Content of the base address register + 28h
Bit
31
30
29
28
27
Symbol
reserved^[1]
Reset
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
Symbol
reserved^[1]
Reset
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
Symbol
reserved^[1]
Reset
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
Symbol
reserved^[1]
IAAE
HSEE
FLRE
Reset
Access
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
26
0
R/W
18
0
R/W
10
0
R/W
2
PCIE
0
R/W
25
24
0
0
R/W
R/W
17
16
0
0
R/W
R/W
9
8
0
R/W
1
USBERR
INTE
0
R/W
0
R/W
0
USBINTE
0
R/W
[1] The reserved bits should always be written with the reset value.
Table 108. USBINTR - USB Interrupt Enable register bit description
Address: Content of the base address register + 28h
Bit
Symbol Description
31 to 6 reserved -
5
IAAE
Interrupt on Asynchronous Advance Enable: When this bit and IAA (bit 5 in the USBSTS
register) are set, the host controller issues an interrupt at the next interrupt threshold. The interrupt
is acknowledged by software clearing bit IAA.
4
HSEE
Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS register) are set, the host
controller issues an interrupt. The interrupt is acknowledged by software clearing bit HSE.
3
FLRE
Frame List Rollover Enable: When this bit and FLR (bit 3 in the USBSTS register) are set, the host
controller issues an interrupt. The interrupt is acknowledged by software clearing bit FLR.
2
PCIE
Port Change Interrupt Enable: When this bit and PCD (bit 2 in the USBSTS register) are set, the
host controller issues an interrupt. The interrupt is acknowledged by software clearing bit PCD.
1
USBERR USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the USBSTS register) are set,
INTE
the host controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged
by software clearing bit USBERRINT.
0
USBINTE USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS register) are set, the host
controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing bit USBINT.
ISP1563_3
Product data sheet
Rev. 03 — 18 November 2008
© NXP B.V. 2008. All rights reserved.
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