ISP1563 Datasheet, PDF (50/103 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

NXP Semiconductors
ISP1563
HS USB PCI host controller
Bit
15
14
13
12
11
Symbol
BCED[11:4]
Reset
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
Symbol
BCED[3:0]
Reset
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
[1] The reserved bits should always be written with the reset value.
10
9
0
0
R/W
R/W
2
1
reserved^[1]
0
0
R/W
R/W
8
0
R/W
0
0
R/W
Table 66. HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description
Address: Content of the base address register + 2Ch
Bit
Symbol
Description
31 to 4
BCED[27:0]
Bulk Current ED: This is advanced to the next ED after the host controller has served the current
ED. The host controller continues processing the list from where it left off in the last frame. When
it reaches the end of the bulk list, the host controller checks CLF (bit 1 of HcCommandStatus). If
the CLF bit is not set, nothing is done. If the CLF bit is set, it copies the content of HcBulkHeadED
to HcBulkCurrentED and clears the CLF bit. The HCD can modify this register only when BLE
(bit 5 in the HcControl register) is cleared. When HcControl is set, the HCD reads the
instantaneous value of this register. This is initially set to logic 0 to indicate the end of the bulk list.
3 to 0 reserved
-
11.1.13 HcDoneHead register
The HcDoneHead register contains the physical address of the last completed TD that
was added to the done queue. In a normal operation, the HCD need not read this register
because its content is periodically written to the HCCA.
Table 67 contains the bit allocation of the register.
Table 67. HcDoneHead - Host Controller Done Head register bit allocation
Address: Content of the base address register + 30h
Bit
31
30
29
28
27
26
25
24
Symbol
DH[27:20]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
DH[19:12]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
DH[11:4]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISP1563_3
Product data sheet
Rev. 03 — 18 November 2008
© NXP B.V. 2008. All rights reserved.
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