ISP1563 Datasheet, PDF (51/103 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

NXP Semiconductors
ISP1563
HS USB PCI host controller
Bit
7
6
5
4
Symbol
DH[3:0]
Reset
0
0
0
0
Access
R/W
R/W
R/W
R/W
[1] The reserved bits should always be written with the reset value.
3
0
R/W
2
1
reserved^[1]
0
0
R/W
R/W
0
0
R/W
Table 68. HcDoneHead - Host Controller Done Head register bit description
Address: Content of the base address register + 30h
Bit
Symbol
Description
31 to 4
DH[27:0]
Done Head: When a TD is completed, the host controller writes the content of HcDoneHead to
the NextTD field of the TD. The host controller then overwrites the content of HcDoneHead with
the address of this TD. This is set to logic 0 whenever the host controller writes the content of
this register to HCCA.
3 to 0
reserved
-
11.1.14 HcFmInterval register
This register contains a 14-bit value that indicates the bit time interval in a frame, that is,
between two consecutive SOFs, and a 15-bit value indicating the full-speed maximum
packet size that the host controller may transmit or receive, without causing a scheduling
overrun. The HCD may carry out minor adjustment on FI (Frame Interval) by writing a new
value over the present at each SOF. This provides the possibility for the host controller to
synchronize with an external clocking resource and to adjust any unknown local clock
offset. The bit allocation of the register is given in Table 69.
Table 69. HcFmInterval - Host Controller Frame Interval register bit allocation
Address: Content of the base address register + 34h
Bit
31
30
29
28
27
26
25
24
Symbol
FIT
FSMPS[14:8]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
FSMPS[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved^[1]
FI[13:8]
Reset
0
0
1
0
1
1
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FI[7:0]
Reset
1
1
0
1
1
1
1
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[1] The reserved bits should always be written with the reset value.
ISP1563_3
Product data sheet
Rev. 03 — 18 November 2008
© NXP B.V. 2008. All rights reserved.
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