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DAC1408D650_1008 Datasheet, PDF (81/98 Pages) NXP Semiconductors – Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
Table 161. LN1_CFG_3 register (address 13h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
LN1_SCR
R
-
4 to 0 LN1_L[4:0]
R
-
Description
scrambling on
number of lanes
Table 162. LN1_CFG_4 register (address 14h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN1_F[7:0]
R
-
Description
number of octets per frame
Table 163. LN1_CFG_5 register (address 15h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
4 to 0 LN1_K[4:0]
R
-
Description
number of frames per multiframe
Table 164. LN1_CFG_6 register (address 16h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN1_M[7:0]
R
-
Description
number of converter per device
Table 165. LN1_CFG_7 register (address 17h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 6 LN1_CS[1:0]
R
-
4 to 0 LN1_N[4:0]
R
-
Description
number of control bits
converter resolution
Table 166. LN1_CFG_8 register (address 18h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
4 to 0 LN1_N’[4:0]
R
-
Description
number of bits per sample
Table 167. LN1_CFG_9 register (address 19h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
4 to 0 LN1_S[4:0]
R
-
Description
number of samples per converter per frame cycle
Table 168. LN1_CFG_10 register (address 1Ah) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 6 LN1_HD
R
-
4 to 0 LN1_CF[4:0]
R
-
Description
high density
number of control words per frame cycle
Table 169. LN1_CFG_11 register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN1_RES1[7:0]
R
-
Description
lane 1 reserved field
DAC1408D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 11 August 2010
© NXP B.V. 2010. All rights reserved.
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