DAC1408D650_1008 Datasheet, PDF (37/98 Pages) NXP Semiconductors – Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating

NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
10.13.4 Phase correction
The Analog Quadrature Modulator which follows the DACs may have a phase imbalance
which will result in undesired sideband. By adjusting the phase between the I and Q
channels, the spur can be reduced.
Without compensation the I and Q have a phase difference of Π/2 (90^o). The registers
Phasecorr_cntrl0 and Phasecorr_cntrl1 located in register page 0 allow a phase variation
from 75,7^o to 104,3^o . The two registers define a signed value that range from −512 to
+511. The resulting phase compensation (in radians) is given by the equation:
Phasecorr_cntrl[9:0] / 2048.
10.14 Power and grounding
The power supplies should be decoupled with the following ground pins to optimize the
decoupling:
• V_DDA(1V8): pin 38 with pin 37; pin 44 with pin 43; pin 11 with pin 12; pin 17 with pin 18;
pin 32 with pin 31.
10.15 Configuration interface
10.15.1 Register description
DAC1408D650 implements indirect addressing using a page access method. The
page-address is located at address 0x1F and is by default 0x00, which selects page 0 as
default page. For example, to access registers which configure the JESDRX, one must
first activate page 4 by writing 0x04 to the page-address 0x1F.
The DAC1408D650 contains six different pages.
The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the
device to its default state is mandatory.
10.15.2 Detailed descriptions of registers
The register information has been provided in page form accompanied by a detailed
description for each bit in the tables following the register allocation map of each page.
DAC1408D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 11 August 2010
© NXP B.V. 2010. All rights reserved.
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