DAC1408D650_1008 Datasheet, PDF (16/98 Pages) NXP Semiconductors – Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating

NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
• if the buffers are empty or overflow, this will be indicated by the registers buff_err_ln0
to buff_err_ln3
10.2.5.2 Multi-device operation
DAC1408D650 implements a multi-device interlane alignment that guarantees a skew of
less than one output period between them.
Two modes are available: Master/slave and All slave. Both make use of the MDS_P and
MDS_N pins.
LANES
ref_A
mds_A_out
COMP
mds_A
MDS_A
I
DIG
BUFFER
Q
SYNC~
CLK
MGMT
DAC
CK
001aal073
Fig 8. Multi-Device Synchronization (MDS) implementation
Each DAC device of the system generates its own reference (ref_A on Figure 8).
If configured as slave, an early-late comparator compares the internal reference with the
external reference provided by the MDS pins. The comparator controls an internal buffer
that is used to delay the samples.
DAC1408D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 11 August 2010
© NXP B.V. 2010. All rights reserved.
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