DAC1408D650_1008 Datasheet, PDF (65/98 Pages) NXP Semiconductors – Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating

NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
Table 97. INIT_SCR_S7T1_LN0 (address 12h) bit description
Bit
Symbol
Access Value
6 to 0 INIT_VALUE_S7_S1_LN0[6:0]
R/W
00h
Description
initialization value for lane 0 descrambler bits s7 : s1
Table 98. INIT_SCR_S15T8_LN1 register (address 13h) bit description
Bit
Symbol
Access Value Description
7 to 0 INIT_VALUE_S15_S8_LN1[7:0]
R/W
00h
initialization value for lane 1 descrambler bits
s15 : s8
Table 99. INIT_SCR_S7T1_LN1 register (address 14h) bit description
Bit
Symbol
Access Value Description
6 to 0 INIT_VALUE_S7_S1_LN1[6:0]
R/W
00h
initialization value for lane 1 descrambler bits s7 : s1
Table 100. INIT_SCR_S15T8_LN2 register (address 15h) bit description
Bit
Symbol
Access Value Description
7 to 0 INIT_VALUE_S15_S8_LN2[7:0]
R/W
00h
initialization value for lane 2 descrambler bits
s15 : s8
Table 101. INIT_SCR_S7T1_LN2 register (address 16h) bit description
Bit
Symbol
Access Value Description
6 to 0 INIT_VALUE_S7_S1_LN2[6:0]
R/W
00h
initialization value for lane 2 descrambler bits s7 : s1
Table 102. INIT_SCR_S15T8_LN3 register (address 17h) bit description
Bit
Symbol
Access Value Description
7 to 0 INIT_VALUE_S15_S8_LN3[7:0]
R/W
00h
initialization value for lane 3 descrambler bits
s15 : s8
Table 103. INIT_SCR_S7T1_LN3 register (address 18h) bit description
Bit
Symbol
Access Value Description
6 to 0 INIT_VALUE_S7_S1_LN3[6:0]
R/W
00h
initialization value for lane 3 descrambler bits s7 : s1
Table 104. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description
Bit
Symbol
Access Value Description
7 to 4 INIT_ILA_BUFPTR_LN1[3:0]
R/W
8h
initialization value for ila bufptr lane 1
3 to 0 INIT_ILA_BUFPTR_LN0[3:0]
R/W
8h
initialization value for ila bufptr lane 0
Table 105. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description
Bit
Symbol
Access Value Description
7 to 4 INIT_ILA_BUFPTR_LN3[3:0]
R/W
8h
initialization value for ila bufptr lane 3
3 to 0 INIT_ILA_BUFPTR_LN2[3:0]
R/W
8h
initialization value for ila bufptr lane 2
DAC1408D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 11 August 2010
© NXP B.V. 2010. All rights reserved.
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