PSMN3R5-30YL Datasheet, PDF (8/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
003aab273
2
a
1.6
1.2
0.8
0.4
0
-60
0
60
120
180
T_j (°C)
V_DS
I_D
V_GS(pl)
V_GS(th)
V_GS
Q_GS1 Q_GS2
Q_GS
Q_GD
Q_G(tot)
003aaa508
Fig 14. Gate charge waveform definitions
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
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10
V_GS
(V)
8
V_DS = 12 (V)
V_DS = 19 (V)
6
4
2
0
0
10
20
30
40
50
Q_G (nC)
3000
C
(pF)
2500
2000
1500
1000
500
0
10^-1
C_iss
C_oss
C_rss
1
003aac719
10 _{VDS (V)} 10²
Fig 15. Gate-source voltage as a function of gate
charge; typical values
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN3R5-30YL_1
Preliminary data sheet
Rev. 01 — 14 October 2008
© NXP B.V. 2008. All rights reserved.
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