PSMN3R5-30YL Datasheet, PDF (1/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

PSMN3R5-30YL
N-channel TrenchMOS logic level FET
Rev. 01 — 14 October 2008
Preliminary data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
„ High efficiency due to low switching
and conduction losses
„ Suitable for logic level gate drive
sources
1.3 Applications
„ Class-D amplifiers
„ DC-to-DC converters
„ Motor control
„ Server power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
V_DS
drain-source voltage T_j ≥ 25 °C; T_j ≤ 150 °C
I_D
drain current
T_mb = 25 °C; V_GS = 10 V;
[1]
see Figure 1;
P_tot
total power
dissipation
T_mb = 25 °C; see Figure 2
Dynamic characteristics
Q_GD
gate-drain charge V_GS = 4.5 V; I_D = 10 A;
V_DS = 12 V; see Figure 14;
see Figure 15
Static characteristics
R_DSon
drain-source
V_GS = 10 V; I_D = 15 A;
on-state resistance T_j = 25 °C; see Figure 12
[1] Continuous current is limited by package.
Min Typ Max Unit
-
-
30 V
-
-
100 A
-
-
74 W
-
5
-
nC
-
2.2 3.5 mΩ