PSMN3R5-30YL Datasheet, PDF (3/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
120
I_D
(A)
100
80
60
40
20
0
0
(1)
50
003aac712
100
150
200
T_mb (°C)
120
P_der
(%)
80
03aa15
40
0
0
50
100
150
200
T_mb (°C)
Fig 1. Continuous drain current as a function of
mounting base temperature
10³
I_D
(A)
10²
Limit R_DSon = V_DS / I_D
10
1
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aac731
10 μs
100 μs
DC
1 ms
10 ms
100 ms
10^-1
10^-1
1
10
10²
V_DS (V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN3R5-30YL_1
Preliminary data sheet
Rev. 01 — 14 October 2008
© NXP B.V. 2008. All rights reserved.
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