TDA8034T Datasheet, PDF (7/29 Pages) NXP Semiconductors – Smart card interface

NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
DIGITAL
enclkin
clkxtal
MULTIPLEXER
CRYSTAL
XTAL1
XTAL2
001aak992
enclkin and clkxtal are internal signal names.
Fig 5. Basic layout for using an external clock
The clock frequency is selected using pin CLKDIV1 to be either ¹âˆ¨₂ f_xtal or ¹âˆ¨₄ f_xtal on
TDA8034T or f_xtal or ¹âˆ¨₂ f_xtal on TDA8034AT as shown in Table 4.
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change has the correct width. When dynamically changing the frequency, the modification
is only effective after 10 clock periods on pin XTAL1.
The duty cycle of f_xtal on pin CLK should be between 45 % and 55 %. If an external clock
is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %.
When the frequency of the clock signal on pin CLK is either ¹âˆ¨₂ f_xtal or ¹âˆ¨₄ f_xtal on
TDA8034T or f_xtal or ¹âˆ¨₂ f_xtal on TDA8034AT, the frequency dividers guarantee a duty
cycle between 45 % and 55 %.
Table 4. Clock configuration
Pin CLKDIV1 level
Pin CLK level
TDA8034T
HIGH
LOW
1_{∨2 fxtal}
1_{∨4 fxtal}
TDA8034AT
1_{∨2 fxtal}
f_xtal
8.4 Input and output circuits
When pins I/O and I/OUC are pulled HIGH using an 11 kΩ resistor between pins I/O and
V_CC and/or between pins I/OUC and V_DD(INTF), both lines enter the idle state. Pin I/O is
referenced to V_CC and pin I/OUC to V_DD(INTF), thus allowing operation at V_CC ≠ V_DD(INTF).
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other line, making it the slave. After a time delay t_d,
the logic 0 present on the master-side is sent to the slave-side. When the master-side
returns logic 1, the slave-side sends logic 1 during time delay (t_w(pu)). After this sequence,
both master and slave sides return to their idle states.
The active pull-up feature ensures fast LOW-to-HIGH transitions making the
TDA8034T/TDA8034AT capable of delivering more than 1 mA, up to an output voltage of
0.9V_CC, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is
dependent on the internal pull-up resistor value and load current. The current sent to and
received from the card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.
TDA8034T_TDA8034AT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0. — 12 November 2010
© NXP B.V. 2010. All rights reserved.
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