PRTR5V0U2D Datasheet, PDF (7/12 Pages) NXP Semiconductors – Ultra low capacitance double rail-to-rail ESD protection

NXP Semiconductors
PRTR5V0U2D
Ultra low capacitance double rail-to-rail ESD protection
7. Application information
Handling data rates up to 480 Mbit/s, USB 2.0 interfaces require ESD protection devices
with an extremely low line capacitance in order to avoid signal distortion.
With a capacitance of only 1 pF, the PRTR5V0U2D offers IEC 61000-4-2,
level 4 compliant ESD protection.
The PRTR5V0U2D integrates two ultra low capacitance rail-to-rail ESD protection
channels and one additional ESD protection diode.
The additional ESD protection diode connected between ground and V_CC prevents
charging of the supply.
USB controller
common mode
D+ ^choke
D−
V_BUS
protected IC/device
V_BUS
D+
D−
GND
006aaa485
Fig 5. Application diagram: USB 2.0
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the PRTR5V0U2D as close to the input terminal or connector as possible.
2. The path length between the PRTR5V0U2D and the protected line should be
minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
PRTR5V0U2D_1
Product data sheet
Rev. 01 — 28 April 2009
© NXP B.V. 2009. All rights reserved.
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