ADC1412D065 Datasheet, PDF (7/37 Pages) NXP Semiconductors – Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1412D065/080/105/125
Dual 14-bit ADC 65, 80, 105 or 125 Msps
6.2.2 Pin description
Table 3. Pin description (LVDS/DDR) digital outputs) ^[1]
Symbol
Pin Type ^[2] Description
DB12_DB13_M 25 O
differential output data DB12 and DB13 multiplexed,
complement
DB12_DB13_P 26 O
differential output data DB12 and DB13 multiplexed, true
DB10_DB11_M 27 O
differential output data DB10 and DB11 multiplexed,
complement
DB10_DB11_P 28 O
differential output data DB10 and DB11 multiplexed, true
DB8_DB9_M 29 O
differential output data DB8 and DB9 multiplexed, complement
DB8_DB9_P 30 O
differential output data DB8 and DB9 multiplexed, true
DB6_DB7_M 33 O
differential output data DB6 and DB7 multiplexed, complement
DB6_DB7_P 34 O
differential output data DB6 and DB7 multiplexed, true
DB4_DB5_M 35 O
differential output data DB4 and DB5 multiplexed, complement
DB4_DB5_P 36 O
differential output data DB4 and DB5 multiplexed, true
DB2_DB3_M 37 O
differential output data DB2 and DB3 multiplexed, complement
DB2_DB3_P 38 O
differential output data DB2 and DB3 multiplexed, true
DB0_DB1_M 39 O
differential output data DB0 and DB1 multiplexed, complement
DB0_DB1_P 40 O
differential output data DB0 and DB1 multiplexed, true
DAVM
41 O
data valid output clock, complement
DAVP
42 O
data valid output clock, true
DA0_DA1_P 43 O
differential output data DA0 and DA1 multiplexed, true
DA0_DA1_M 44 O
differential output data DA0 and DA1 multiplexed, complement
DA2_DA3_P 45 O
differential output data DA2 and DA3 multiplexed, true
DA2_DA3_M 46 O
differential output data DA2 and DA3 multiplexed, complement
DA4_DA5_P 47 O
differential output data DA4 and DA5 multiplexed, true
DA4_DA5_M 48 O
differential output data DA4 and DA5 multiplexed, complement
DA6_DA7_P 51 O
differential output data DA6 and DA7 multiplexed, true
DA6_DA7_M 52 O
differential output data DA6 and DA7 multiplexed, complement
DA8_DA9_P 53 O
differential output data DA8 and DA9 multiplexed, true
DA8_DA9_M 54 O
differential output data DA8 and DA9 multiplexed, complement
DA10_DA11_P 55 O
differential output data DA10 and DA11 multiplexed, true
DA10_DA11_M 56 O
differential output data DA10 and DA11 multiplexed,
complement
DA12_DA13_P 57 O
differential output data DA12 and DA13 multiplexed, true
DA12_DA13_M 58 O
differential output data DA12 and DA13 multiplexed,
complement
[1] Pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs
(see Table 2).
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
ADC1412D065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
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