ADC1412D065 Datasheet, PDF (15/37 Pages) NXP Semiconductors – Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1412D065/080/105/125
Dual 14-bit ADC 65, 80, 105 or 125 Msps
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, 2’s
complement or gray code; see Table 22) or using pin DFS in PIN control mode (offset
binary or 2’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, 2’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1412D supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V_I(cm)) on pins INAP, INAM, INBP and INBM set to 0.5V_DDA.
The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 21 further details).
The equivalent circuit of the sample and hold input stage, including ESD protection and
circuit and package parasitics, is shown in Figure 8.
INAP/INBP
INAM/INBM
Package
ESD
Parasitics
Switch
Ron = 14 Ω
4 pF
internal
clock
Sampling
Capacitor
Switch
Ron = 14 Ω
4 pF
internal
clock
Sampling
Capacitor
Fig 8. Input sampling circuit
005aaa092
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in Figure 9 is needed to counteract the effects of charge
injection generated by the sampling capacitance.
ADC1412D065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
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