ADC1412D065 Datasheet, PDF (19/37 Pages) NXP Semiconductors – Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1412D065/080/105/125
Dual 14-bit ADC 65, 80, 105 or 125 Msps
11.3.2 Gain control
The gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see
Table 21). This makes it possible to improve the Spurious-Free Dynamic Range (SFDR) of
the ADC1412D. The corresponding full scale input voltage range varies between 2 V (p-p)
and 1 V (p-p), as shown in Table 13:
Table 13.
INTREF
000
001
010
011
100
101
110
111
Reference SPI Gain Control
Gain
0 dB
−1 dB
−2 dB
−3 dB
−4 dB
−5 dB
−6 dB
reserved
full scale (p-p)
2V
1.78 V
1.59 V
1.42 V
1.26 V
1.12 V
1V
x
11.3.3
Common-mode output voltage (V_O(cm))
A 0.1 µF filter capacitor should be connected between pin VCMA/VCMB and ground to
ensure a low-noise common-mode output voltage. When AC-coupled, pin VCMA/VCMB
can then be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
VCMA/VCMB
1.5 V
0.1 µF
PACKAGE ESD PARASITICS
COMMON MODE
REFERENCE
ADC CORE
Fig 17. Equivalent schematic of the common-mode reference circuit
005aaa099
11.3.4 Biasing
The common-mode input voltage (V_I(cm)) on pins INAP/INBP and INAM/INBM should be
set externally to 0.5V_DDA for optimal performance and should always be between 0.9 V
and 2 V.
The graph in Figure 18 illustrates how the SFDR and SNR characteristics vary with
changes in the common-mode input voltage.
ADC1412D065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
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