ADC1412D065 Datasheet, PDF (21/37 Pages) NXP Semiconductors – Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1412D065/080/105/125
Dual 14-bit ADC 65, 80, 105 or 125 Msps
Sine
Clock lnput
CLKP
CLKM
Sine
Clock lnput
Fig 20. Sine differential clock input
CLKP
CLKM
005aaa054
LVDS
Clock lnput
CLKP
CLKM
Fig 21. LVDS differential clock input
005aaa055
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 22. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
PACKAGE ESD PARASITICS
CLKP
CLKM
Vcm(clk)
SE_SEL SE_SEL
5k
5k
Fig 22. Equivalent Input circuit
005aaa056
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
bit SE_SEL.
ADC1412D065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
21 of 37