UJA1061 Datasheet, PDF (63/74 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

NXP Semiconductors
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
Table 27. Dynamic characteristics^[1] (Continued)
T_vj = −40 °C to + 150 °C; V_BAT42 = 5.5 V to 52 V; V_BAT14 = 5.5 V to 27 V; V_BAT42 ≥ V_BAT14 − 1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Battery monitoring
t_BAT42(L)
BAT42 LOW time for
setting PWONS
5
-
20
µs
Power supply V1; pin V1
t_V1(CLT)
V1 clamped LOW
time during ramp-up
of V1
Start-up mode; V1 active
229
-
283
ms
Power supply V2; pin V2
t_V2(CLT)
V2 clamped LOW
time during ramp-up
of V2
V2 active
28
-
36
ms
Power supply V3; pin V3
t_W(CS)
cyclic sense period
V3C = 10; see Figure 13
V3C = 11; see Figure 13
14
-
28
-
18
ms
36
ms
t_on(CS)
cyclic sense on-time V3C = 10; see Figure 13
V3C = 11; see Figure 13
345
-
345
-
423
µs
423
µs
Wake-up input; pin WAKE
t_WU(ipf)
t_su(CS)
input port filter time V_BAT42 = 5 V to 27 V
5
-
V_BAT42 = 27 V to 52 V
30
-
cyclic sense sample V3C = 11 or 10; see Figure 13
310
-
setup time
120
µs
250
µs
390
µs
Watchdog
t_WD(ETP)
earliest watchdog
trigger point
programmed Nominal
Watchdog Period (NWP);
Normal mode
0.45 ×
-
NWP
0.55 ×
NWP
t_WD(LTP)
latest watchdog
trigger point
programmed nominal
watchdog period; Normal
mode, Standby mode and
Sleep mode
0.9 × NWP -
1.1 × NWP
t_WD(init)
watchdog initializing watchdog time-out in Start-up
229
-
period
mode
283
ms
Fail-safe mode
t_ret
retention time
Fail-safe mode; wake-up
1.3
1.5
1.7
s
detected
Reset output; pin RSTN
t_RSTN(CHT)
clamped HIGH time, RSTN driven LOW internally
pin RSTN
but RSTN pin remains HIGH
115
-
141
ms
t_RSTN(CLT)
clamped LOW time, RSTN driven HIGH internally
pin RSTN
but RSTN pin remains LOW
229
-
283
ms
t_RSTN(INT)
interrupt monitoring INTN = 0
time
229
-
283
ms
UJA1061_5
Product data sheet
Rev. 05 — 22 November 2007
© NXP B.V. 2007 Nov 23. All rights reserved.
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