UJA1061 Datasheet, PDF (30/74 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

NXP Semiconductors
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
Table 6.
Bit
11 to 6
Mode register bit description (bits 11 to 6)^[1] (Continued)
Symbol
Description
Value
Time
Normal
mode (ms)
NWP[5:0] Nominal
00 1001
6
Watchdog Period _{00 1100}
12
WDPRE = 01 (as _{01 0010}
24
set in the Special
Mode register) ^{01 0100}
48
01 1011
60
10 0100
72
10 1101
84
11 0011
96
11 0101
108
11 0110
120
Nominal
00 1001
10
Watchdog Period _{00 1100}
20
WDPRE = 10 (as
set in the Special
01 0010
40
Mode register) ^{01 0100}
80
01 1011
100
10 0100
120
10 1101
140
11 0011
160
11 0101
180
11 0110
200
Nominal
001001
14
Watchdog Period ₀₀₁₁₀₀
28
WDPRE = 11 (as
set in the Special
010010
56
Mode register) ⁰¹⁰¹⁰⁰
112
011011
140
100100
168
101101
196
110011
224
110101
252
110110
280
Standby
mode (ms)
30
60
120
240
480
960
1536
3072
6144
OFF^[2]
50
100
200
400
800
1600
1560
5120
10240
OFF^[2]
70
140
280
560
1120
2240
3584
7168
14336
OFF^[2]
Flash mode
(ms)
30
60
120
240
480
960
1536
3072
6144
12288
50
100
200
400
800
1600
1560
5120
10240
20480
70
140
280
560
1120
2240
3584
7168
14336
28672
Sleep mode
(ms)
240
480
960
1536
3072
4608
6144
9216
12288
OFF^[3]
400
800
1600
2560
5120
7680
10240
15360
20480
OFF^[3]
560
1120
2240
3584
7168
10752
14336
21504
28672
OFF^[3]
[1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f_osc = 512 kHz.
[2] See Section 6.4.4.
[3] The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is
immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry
without dips on V1; see Section 6.4.4.
UJA1061_5
Product data sheet
Rev. 05 — 22 November 2007
© NXP B.V. 2007 Nov 23. All rights reserved.
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