UJA1061 Datasheet, PDF (1/74 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
Rev. 05 — 22 November 2007
Product data sheet
1. General description
The UJA1061 fail-safe System Basis Chip (SBC) replaces basic discrete components
which are common in every Electronic Control Unit (ECU) with a Controller Area Network
(CAN) and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all
networking applications which control various power and sensor peripherals by using
fault-tolerant CAN as the main network interface and LIN as a local sub-bus. The fail-safe
SBC contains the following integrated devices:
• ISO11898-3 compliant fault-tolerant CAN transceiver, interoperable with TJA1054,
TJA1054A and TJA1055
• LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
• Advanced independant watchdog
• Dedicated voltage regulators for microcontroller and CAN transceiver
• Serial peripheral interface (full duplex)
• Local wake-up input port
• Inhibit / limp home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
• Advanced low power concept
• Safe and controlled system start-up behavior
• Advanced fail-safe system behavior that prevents any conceivable deadlock
• Detailed status reporting on system and sub-system levels
The UJA1061 is designed to be used in combination with a microcontroller with a CAN
controller. The fail-safe SBC ensures that the microcontroller is always started up in a
defined manner. In failure situations the fail-safe SBC will maintain the microcontroller
function for as long as possible, to provide full monitoring and software driven fall-back
operation.
The UJA1061 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.