UJA1061 Datasheet, PDF (55/74 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

NXP Semiconductors
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
10
I_BAT14 − I_V1
(mA)
8
6
4
V_BAT14 = 8 V⁽¹⁾
2
5.5 V⁽²⁾
0
0
−50
−100
(1) Types 5V0, 3V3 and 3V0.
(2) Type 5V0 only.
a. At T_j = −40 °C, +25 °C and +150 °C.
5
I_BAT14 − I_V1
(mA)
4
T_j = +150 °C
001aaf246
T_j = −40 °C
+25 °C
+150 °C
+25 °C
−40 °C
−150
−200
−250
I_V1 (mA)
001aaf247
3
V_BAT14 = 9 V to 27 V⁽¹⁾
2
5.5 V⁽²⁾
1
0
0
−50
−100
−150
−200
−250
I_V1 (mA)
(1) Types 5V0, 3V3 and 3V0.
(2) Types 3V3 and 3V0.
b. At T_j = −40 °C to +150 °C.
Fig 17. V1 quiescent current as a function of output current
UJA1061_5
Product data sheet
Rev. 05 — 22 November 2007
© NXP B.V. 2007 Nov 23. All rights reserved.
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