DAC1408D650 Datasheet, PDF (60/88 Pages) NXP Semiconductors – Dual 14-bit DAC, up to 650 Msps, 2´ and 4´ interpolating with JESD204A interface

NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2× and 4× interpolating
Table 92. ERROR_HANDLING register (address 1Bh) bit description
Default settings are shown highlighted.
Bit Symbol
Access Value Description
6
NAD_ERR_CORR R/W
0
nit-errors passed to frame-assembler (fa‘)
1
nad(nit- and disparity)-errors passed to fa
5
KUX_CORR
R/W
0
unexpected k-character errors ignored (@fa)
01
unexpected k-character errors
concealment(2fa)
4
NAD_CORR
R/W
0
nad-errors ignored (@fa)
1
nad-errors concealment (@fa)
3 to 2 CORR_MODE[1:0] R/W
00
conceal 1 period @ fa
01
conceal 2 periods @ fa
10
conceal 3 periods @ fa
11
conceal 4 periods @ fa
1
IMPL_ALT
R/W
0
default disparity error detection (table-mode)
01
alternative disparity error detection (cnt-mode)
0
IGNORE_ERR
R/W
0
no action
1
ignore disparity/nit-errors @ lane-controller
Table 93. PAGE_ADDRESS register (address 1Fh) bit description
Bit Symbol
Access Value Description
2 to 0 PAGE
R/W -
page_address
DAC1408D650_1
Objective data sheet
Rev. 01 — 26 May 2009
© NXP B.V. 2009. All rights reserved.
60 of 88