DAC1408D650 Datasheet, PDF(1/88 Page) NXP Semiconductors – Dual 14-bit DAC, up to 650 Msps, 2´ and 4´ interpolating with JESD204A interface

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DAC1408D650 Datasheet, PDF (1/88 Pages) NXP Semiconductors – Dual 14-bit DAC, up to 650 Msps, 2´ and 4´ interpolating with JESD204A interface

DAC1408D650

Dual 14-bit DAC, up to 650 Msps, 2Ã and 4Ã interpolating with

JESD204A interface

Rev. 01 â 26 May 2009

Objective data sheet

1. General description

The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC)

with selectable 2Ã or 4Ã interpolating ï¬lters optimized for multi-carriers WCDMA

transmitters.

Thanks to its digital on-chip modulation, the DAC1408D650 allows the complex I and Q

inputs to be converted up from baseband to IF. The mixing frequency is adjusted via a

Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and

the phase is controlled by a 16-bit register.

The DAC1408D650 also includes a 2Ã and 4Ã clock multiplier which provides the

appropriate internal clocks and an internal regulation to adjust the output full scale

current.

The input data format is serial according to JESD204A speciï¬cation. This new interface

has numerous advantages over the traditional parallel one: easy PCB layout, lower

radiated noise, lower pin count, self-synchronous link, skew compensation.

DAC1408D650 maximum number of lanes is 4 and its maximum serial data rate is

3.25 Gbps.

2. Features

I Dual 14-bit resolution

I 650 Msps maximum update rate

I Four JESD204A serial input lanes

I SFDR: â75 dBc; fs = 640 Msps;

fo = 4 MHz

I IMD3: 74 dBc; fs = 640 Msps;

fo = 154 MHz

I Inverse (sin x) / x function

I Differential CML receiver with

I Embedded complex modulator

termination

I LMF = 421 or LMF = 211 support

I 3 or 4 wire SPI conï¬guration interface

I Input data rate up to 325 Msps or

I Differential scalable output current from

162.5 Msps

1.6 mA to 22 mA

I Selectable 2Ã or 4Ã interpolation ï¬lters I External analog offset control

(10-bit auxiliary DACs)

I Twoâs complement or Binary Offset I Internal digital offset control

Data Format (BODF)

I Very low noise cap free integrated PLL I On-chip 1.25 V reference

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