DAC1408D650 Datasheet, PDF (50/88 Pages) NXP Semiconductors – Dual 14-bit DAC, up to 650 Msps, 2´ and 4´ interpolating with JESD204A interface

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10.15.2.5 Page 4 allocation map description
Table 65. Page 4 register allocation map
Address Register name R/W Bit definition
Default
b7
b6
b5
b4
b3
b2
b1
b0
Bin
Hex
0 00h SR_DLP_0
R/W SR_SWA_ SR_SWA_ SR_SWA_ SR_SWA_ SR_CA_LN3 SR_CA_LN2 SR_CA_LN1 SR_CA_LN0 00000000 00h
LN3
LN2
LN1
LN0
1 01h SR_DLP_1
R/W SR_CNTRL SR_CNTRL SR_CNTRL_ SR_CNTRL_ SR_DEC_LN SR_DEC_LN SR_DEC_LN SR_DEC_LN 00000000 00h
_LN3
_LN2
LN1
LN0
3
2
1
0
2 02h FORCE_LOCK R/W FORCE_ FORCE_ FORCE_ FORCE_
-
-
-
SR_ILA 00000000 00h
LOCK_LN3 LOCK_LN2 LOCK_LN1 LOCK_LN0
3 03h MAN_LOCK_ R/W
LN_1_0
MAN_LOCK_LN1[3:0]
MAN_LOCK_LN0[3:0]
00000000 00h
4 04h MAN_LOCK_2_0 R/W
MAN_LOCK_LN3[3:0]
MAN_LOCK_LN2[3:0]
00000000 00h
5 05h CA_CNTRL
R/W WORD_ WORD_ WORD_ WORD_ SELECT_RF SELECT_RF SELECT_RF SELECT_RF 00000000 00h
SWAP_LN3 SWAP_LN2 SWAP_LN1 SWAP_LN0 _F10_LN3 _F10_LN2 _F10_LN1 _F10_LN0
6 06h SCR-CNTRL
R/W MAN_SCR MAN_SCR_ MAN_SCR_ MAN_SCR_ FORCE_ FORCE_ FORCE_ FORCE_ 00000000 00h
_LN3
LN2
LN1
LN0
SRC_LN3 SRC_LN2 SRC_LN1 SRC_LN0
7 07h ILA_CNTRL
R/W SEL_421_
211
SEL_ILA[1:0]
SEL_LOCK[2:0]
SUP_LANE_ EN_SCR 10000011 83h
SYN
8 08h FORCE_ALIGN R/W
-
-
-
-
-
-
DYN_ALIGN FORCE_ALI 00000000 00h
_ENA
GN
9 09h MAN_ALIGN_ R/W
LN_0_1
MAN_ALIGN_LN1[3:0]
MAN_ALIGN_LN0[3:0]
00000000 00h
10 0Ah MAN_ALIGN_ R/W
LN_1_2
MAN_ALIGN_LN3[3:0]
MAN_ALIGN_LN2[3:0]
00000000 00h
11 0Bh FA_ERR_
HANDLING
R/W SEL_KOUT_UNEXP_LN SEL_KOUT_UNEXP_LN1 SEL_NIT_ERR_LN23
23
0
SEL_NIT_ERR_LN10 00000000 00h
12 0Ch SYNCOUT_
R/W
MODE
SEL_RE_INIT[2:0]
SYNC_POL
SEL_SYNC[3:0]
00000000 00h
13 0Dh LANE_
R/W
-
-
-
-
POL_LN3 POL_LN2 POL_LN1 POL_LN0 00000000 00h
POLARITY
14 OEh LANE_SELECT R/W LANE_SEL_LN3[1:0] LANE_SEL_LN2[1:0]
LANE_SEL_LN1[1:0]
LANE_SEL_LN0[1:0] 11100100 E4h
16 10h SOFT_RESET_ R/W
-
-
-
-
SR_SCR_LN SR_SCR_LN SR_SCR_LN SR_SCR_LN 00000000 00h
SCRAMBLER
3
2
1
0
17 11h INIT_SCR_S15T8 R/W
_LN0
INIT_VALUE_S15_S8_LN0[7:0]
00000000 00h