MCIMX6DP5EYM1AA Datasheet, PDF (58/168 Pages) NXP Semiconductors – i.MX 6DualPlus/6QuadPlus Automotive Applications Processors

Electrical Characteristics
4.9.3.4 General EIM Timing-Asynchronous Mode
Figure 18 through Figure 22 and Table 41 provide timing parameters relative to the chip select (CS) state
for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing
parameters mentioned above.
Asynchronous read and write access length in cycles may vary from what is shown in Figure 18 through
Figure 21 as RWSC, OEN & CSN is configured differently. See the i.MX 6DualPlus/6QuadPlus reference
manual (IMX6DQPRM) for the EIM programming model.
start of
access
end of
access
INT_CLK
MAXCSO
EIM_CSx_B
EIM_ADDRxx/
EIM_ADxx
WE31
Last Valid Address
Address V1
WE32
Next Address
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_DATA[07:00]
WE39
WE40
WE35
WE36
WE37
WE38
MAXCO
D(V1)
WE43
MAXDI
Figure 18. Asynchronous Memory Read Access (RWSC = 5)
WE44
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 1, 03/2016
58
Freescale Semiconductor Inc.