MCIMX6DP5EYM1AA Datasheet, PDF (110/168 Pages) NXP Semiconductors – i.MX 6DualPlus/6QuadPlus Automotive Applications Processors

Electrical Characteristics
4.11.11 LVDS Display Bridge (LDB) Module Parameters
The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD
644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.”
Table 71. LVDS Display Bridge (LDB) Electrical Specification
Parameter
Symbol
Test Condition
Min
Differential Voltage Output Voltage V_OD 100 Ω Differential load
250
Output Voltage High
Voh 100 Ω differential load
1.25
(0 V Diff—Output High Voltage static)
Output Voltage Low
Vol 100 Ω differential load
0.9
(0 V Diff—Output Low Voltage static)
Offset Static Voltage
V_OS Two 49.9 Ω resistors in series between N-P
1.15
terminal, with output in either Zero or One state, the
voltage measured between the 2 resistors.
VOS Differential
Output short-circuited to GND
V_OSDIFF Difference in V_OS between a One and a Zero state -50
ISA ISB With the output common shorted to GND
-24
VT Full Load Test
VTLoad 100 Ω Differential load with a 3.74 kΩ load between 247
GND and I/O supply voltage
Max Units
450 mV
1.6
V
1.25 V
1.375 V
50 mV
24 mA
454 mV
4.11.12 MIPI D-PHY Timing Parameters
This section describes MIPI D-PHY electrical specifications, compliant with MIPI CSI-2 version 1.0,
D-PHY specification Rev. 1.0 (for MIPI sensor port x4 lanes) and MIPI DSI Version 1.01, and D-PHY
specification Rev. 1.0 (and also DPI version 2.0, DBI version 2.0, DSC version 1.0a at protocol layer) (for
MIPI display port x2 lanes).
4.11.12.1 Electrical and Timing Information
Table 72. Electrical and Timing Information
Symbol
Parameters
Test Conditions
Min Typ Max Unit
V_I
V_LEAK
V_GNDSH
V_OH(absmax)
t_voh(absmax)
Input DC Specifications—Apply to DSI_CLK_P/_N and DSI_DATA_P/_N Inputs
Input signal voltage range
Transient voltage range is limited from -300
mV to 1600 mV
-50 —
Input leakage current
Ground Shift
Maximum transient output
voltage level
Maximum transient time
above VOH(absmax)
VGNDSH(min) = VI = VGNDSH(max) +
VOH(absmax)
Lane module in LP Receive Mode
—
—
—
-10 —
-50 —
——
——
1350 mV
10 mA
50 mV
1.45 V
20 ns
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 1, 03/2016
110
Freescale Semiconductor Inc.