DAC1627D1G25 Datasheet, PDF (53/69 Pages) NXP Semiconductors – Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 76. DAC_PON_SLEEP register (address 16h) bit description …continued
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
2
DAC_A_SLEEP
R
DAC B mode selection
0
normal operation
1
Sleep mode
1
DAC_A_COM_PD
R
commutator A control
0
disable (power-down)
1
enable
0
DAC_A_BLEED_PD
R
DAC A bleed current control
0
disable (power-down)
1
enable
Table 77. DAC_TEST_8 register (address 17h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
2 to 0 PLL_DIG_DELAY[2:0]
R/W
-
digital clock delay offset of PLL/CKGEN_DIV8
Table 78. SPI_PAGE register (address 1Fh) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
2 to 0 PAGE[2:0]
R/W
-
Description
SPI page address
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
53 of 69