DAC1627D1G25 Datasheet, PDF (19/69 Pages) NXP Semiconductors – Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
50 Ω
3.3 V
CML
Z = 50 Ω
Z = 50 Ω
50 Ω
3.3 V
100 nF _CLKP
DAC1627D
100 nF _CLKN
001aan831
Fig 12. DAC core clock: CML configuration with AC-coupling
200 Ω
PECL
Z = 50 Ω
Z = 50 Ω
200 Ω
100 nF _CLKP
100 Ω DAC1627D
100 nF _CLKN
001aan832
Fig 13. DAC core clock: PECL configuration with AC-coupling
10.6 Timing
The DAC1627D1G25 can operate at an update rate (f_s) of up to 1.25 Gsps and with an
input data rate (f_data) of up to 312.5 MHz.
The sampling position of the LVDS data can be tuned using a 16-step compensation delay
clock. The delay clock (see Figure 14, signals LDCLKPcp and LDCLKNcp) is used
internally to obtain a control signal, which enables calibrating the compensation delay at
start-up and monitoring if the sampling position is properly aligned.
Figure 14 shows how the compensation delay helps to recover the LVDS DDR data on
both the A and B paths.
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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