DAC1627D1G25 Datasheet, PDF (52/69 Pages) NXP Semiconductors – Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 72. DAC_CURRENT_4 register (address 13h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0 DAC_CK_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 73. DAC_CURRENT_5 register (address 14h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0 DAC_CAS_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 74. DAC_CURRENT_6 register (address 15h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0 DAC_BLD_BIAS[3:0]
R/W
-
bias current control (see Table 75)
Table 75. Bias current control table
BIAS[3:0]
000
001
010
011
100
101
110
111
Deviation from nominal current
−30 %
−20 %
−10 %
0%
+10 %
+20 %
+30 %
+40 %
Table 76. DAC_PON_SLEEP register (address 16h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
7
DAC_B_PON
R/W
-
DAC B power control
0
power-down
1
power on
6
DAC_B_SLEEP
R
DAC B mode selection
0
normal operation
1
Sleep mode
5
DAC_B_COM_PD
R
commutator B control
0
disable (power-down)
1
enable
4
DAC_B_BLEED_PD
R
DAC B bleed current control
0
disable (power-down)
1
enable
3
DAC_A_PON
R
DAC A power control
0
power-down
1
power on
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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