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PSMN5R0-80PS Datasheet, PDF (5/13 Pages) NXP Semiconductors – N-channel 80 V 4.7 mΩ standard level MOSFET
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NXP Semiconductors
PSMN5R0-80PS
N-channel 80 V 4.7 mΩ standard level MOSFET
6. Characteristics
Table 6. Characteristics
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source
breakdown voltage
gate-source threshold
voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 11; see Figure 12
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 11; see Figure 12
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11; see Figure 12
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 80 V; VGS = 0 V; Tj = 25 °C
VDS = 80 V; VGS = 0 V; Tj = 125 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 15 A; Tj = 100 °C;
see Figure 13
VGS = 10 V; ID = 15 A; Tj = 25 °C
RG
internal gate resistance f = 1 MHz
(AC)
Dynamic characteristics
QG(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 25 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS
QGS(th)
gate-source charge
pre-threshold
gate-source charge
ID = 25 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS(th-pl) post-threshold
gate-source charge
QGD
VGS(pl)
gate-drain charge
gate-source plateau
voltage
ID = 25 A; VDS = 40 V
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; see Figure 16
Crss
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
turn-off delay time
fall time
VDS = 12 V; RL = 0.5 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω
Min Typ Max Unit
73
80
1
-
2
-
-
-
-
-
[2] -
-
-
-
V
-
-
V
-
-
V
-
4.6 V
3
4
V
-
8
µA
-
150 µA
-
100 nA
-
100 nA
-
7
mΩ
3.7 4.7 mΩ
0.95 -
Ω
-
87
-
nC
-
101 -
nC
-
26
-
nC
-
18
-
nC
-
8
-
nC
-
21
-
nC
-
4.2 -
V
-
6793 -
pF
-
913 -
pF
-
350 -
pF
-
33
-
ns
-
21
-
ns
-
73
-
ns
-
14
-
ns
PSMN5R0-80PS_2
Product data sheet
Rev. 02 — 23 June 2009
© NXP B.V. 2009. All rights reserved.
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