74ABT16821A Datasheet, PDF (5/16 Pages) NXP Semiconductors – 20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
1OE, 2OE
1Q0 to 1Q9
GND
V_CC
2Q0 to 2Q9
2CP, 1CP
2D0 to 2D9
1D0 to1D9
Pin
Description
1, 28
output enable input (active LOW)
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
data output
4, 11, 18, 25, 32, 39, 46, 53
ground (0 V)
7, 22, 35, 50
supply voltage
15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data output
29, 56
clock pulse input (active rising edge)
42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data input
55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data input
6. Functional description
Table 3. Function table^[1]
Input
nOE
nCP
nDx
L
↑
l
L
↑
h
L
H or L
X
H
L or H
X
H
↑
Dn
Output
nQ0 to nQ9
L
H
NC
Z
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
↑ = LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
Internal register Operating mode
L
load + read register
H
load + read register
NC
hold
NC
disable output
Dn
disable output
74ABT16821A_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 March 2010
© NXP B.V. 2010. All rights reserved.
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