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| 74ABT16821A Datasheet, PDF (10/16 Pages) NXP Semiconductors – 20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State | |||
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NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
VI
nDx
0V
VI
CP
0V
VM
VM
tsu(H) th(H)
VM
VM
VM
tsu(L) th(L)
VM
001aae860
Fig 7.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM = 1.5 V
Set-up and hold times data input (nDx) to clock (CP)
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
90 %
VM
10 %
tr
tf
90 %
VM
10 %
tW
001aai298
VI
G
VCC
VO
DUT
RT
a. Input pulse definition
b. Test circuit
Fig 8.
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Load circuitry for switching times
VEXT
RL
CL
RL
mna616
Table 8.
Input
VI
3.0 V
Test data
fI
1 MHz
tW
500 ns
tr, tf
⤠2.5 ns
Load
CL
50 pF
RL
500 Ω
VEXT
tPHL, tPLH
open
tPZH, tPHZ
open
tPZL, tPLZ
7.0 V
74ABT16821A_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 â 16 March 2010
© NXP B.V. 2010. All rights reserved.
10 of 16
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