PCAL6524HEAZ Datasheet, PDF(40/69 Page) NXP Semiconductors – Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset

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PCAL6524HEAZ Datasheet, PDF (40/69 Pages) NXP Semiconductors – Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset

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NXP Semiconductors

PCAL6524

Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander

Glitches in the power supply can also affect the power-on reset performance of this

device. The glitch width (tw(gl)VDD) and glitch height (ïVDD(gl)) are dependent on each

other. The bypass capacitance, source impedance, and device impedance are factors that

affect power-on reset performance. Figure 25 and Table 60 provide more information on

how to measure these specifications.

VDD(P)

âVDD(gl)

tw(gl)VDD

time

002aag962

Fig 25. Glitch width and glitch height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition

is released and all the registers and the I2C-bus/SMBus state machine are initialized to

their default states. The value of VPOR differs based on the VDD being lowered to or from

0 V. Figure 26 and Table 60 provide more details on this specification.

VDD(P)

VPOR (rising VDD(P))

VPOR (falling VDD(P))

POR

time

Fig 26. Power-on reset voltage (VPOR)

time

002aag963

8.3 Device current consumption with internal pull-up and pull-down

resistors

The PCAL6524 integrates programmable pull-up and pull-down resistors to eliminate

external components when pins are configured as inputs and pull-up or pull-down

resistors are required (for example, nothing is driving the inputs to the power supply rails.

Since these pull-up and pull-down resistors are internal to the device itself, they contribute

to the current consumption of the device and must be considered in the overall system

design.

The pull-up or pull-down function is selected in registers 50h, 51h and 52h, while the

resistor is connected by the enable registers 4Ch, 4Dh and 4Eh. The configuration of the

resistors is shown in Figure 11.

If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow from

the VDD(P) pin through the resistor to ground when the pin is held LOW. This current will

appear as additional IDD upsetting any current consumption measurements.

PCAL6524

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.1 â 21 September 2016

40 of 69

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