PCAL6524HEAZ Datasheet, PDF (19/69 Pages) NXP Semiconductors – Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset

NXP Semiconductors
PCAL6524
Ultra low-voltage translating 24-bit Fm+ I²C-bus/SMBus I/O expander
6.5.7 Pull-up/pull-down enable registers (4Ch, 4Dh, 4Eh)
The pull-up and pull-down enable registers allow the user to enable or disable
pull-up/pull-down resistors on the I/O pins. Setting the bit to logic 1 enables the selection
of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pull-down
resistors from the I/O pins. Also, the resistors will be disconnected when the outputs are
configured as open-drain outputs (see Section 6.5.11 and Section 6.5.15). Use the
pull-up/pull-down registers to select either a pull-up or pull-down resistor. A register group
write operation is described in Section 7.1. A register group read operation is described in
Section 7.2.
Table 28.
Bit
Symbol
Default
Pull-up/pull-down enable port 0 register (address 4Ch)
7
6
5
4
3
2
PE0.7 PE0.6 PE0.5 PE0.4 PE0.3 PE0.2
0
0
0
0
0
0
1
PE0.1
0
0
PE0.0
0
Table 29.
Bit
Symbol
Default
Pull-up/pull-down enable port 1 register (address 4Dh)
7
6
5
4
3
2
PE1.7 PE1.6 PE1.5 PE1.4 PE1.3 PE1.2
0
0
0
0
0
0
1
PE1.1
0
0
PE1.0
0
Table 30.
Bit
Symbol
Default
Pull-up/pull-down enable port 2 register (address 4Eh)
7
6
5
4
3
2
PE2.7 PE2.6 PE2.5 PE2.4 PE2.3 PE2.2
0
0
0
0
0
0
1
PE2.1
0
0
PE2.0
0
6.5.8 Pull-up/pull-down selection registers (50h, 51h, 52h)
The I/O port can be configured to have pull-up or pull-down resistor by programming the
pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up
resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that
I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no
effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
A register group write operation is described in Section 7.1. A register group read
operation is described in Section 7.2.
Table 31.
Bit
Symbol
Default
Pull-up/pull-down selection port 0 register (address 50h)
7
6
5
4
3
2
PUD0.7 PUD0.6 PUD0.5 PUD0.4 PUD0.3 PUD0.2
1
1
1
1
1
1
1
PUD0.1
1
0
PUD0.0
1
Table 32.
Bit
Symbol
Default
Pull-up/pull-down selection port 1 register (address 51h)
7
6
5
4
3
2
PUD1.7 PUD1.6 PUD1.5 PUD1.4 PUD1.3 PUD1.2
1
1
1
1
1
1
1
PUD1.1
1
0
PUD1.0
1
PCAL6524
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 21 September 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
19 of 69