PCAL6524HEAZ Datasheet, PDF (35/69 Pages) NXP Semiconductors – Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset

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data into port 0
data into port 1
data into port 2
DATA 00
t_h(D)
DATA 10
DATA 01
DATA 20
DATA 02
t_su(D)
t_h(D)
DATA 11
DATA 21
INT
t_v(INT)
t_rst(INT)
SCL 1 2 3 4 5 6 7 8 9
R/W
slave address
I0.x
I1.x
SDA S 0 1 0 0 0 A1 A0 1 A
DATA 00
A
DATA 10
A
START condition
read from port 0
acknowledge
from slave
acknowledge
from master
acknowledge
from master
read from port 1
read from port 2
DATA 03
t_su(D)
DATA 22
I2.x
DATA 22
A
acknowledge
from master
DATA 12
I0.x
STOP condition
DATA 03
1P
non acknowledge
from master
aaa-008809
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 17).
Fig 19. Read input port register (non-latched), scenario 2