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PCAL6524HEAZ Datasheet, PDF (16/69 Pages) NXP Semiconductors – Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset
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NXP Semiconductors
PCAL6524
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 12.
Bit
Symbol
Default
Output port 2 register (address 06h)
7
6
5
4
O2.7
O2.6
O2.5
O2.4
1
1
1
1
3
O2.3
1
2
O2.2
1
1
O2.1
1
0
O2.0
1
6.5.3 Polarity inversion registers (08h, 09h, 0Ah)
The Polarity inversion registers (registers 08h, 09h, 0Ah) allow polarity inversion of pins
defined as inputs by the Configuration register. If a bit in these registers is set (written with
‘1’), the corresponding port pin’s polarity is inverted in the input register. If a bit in this
register is cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A
register group write is described in Section 7.1 and a register group read is described in
Section 7.2.
Table 13.
Bit
Symbol
Default
Polarity inversion port 0 register (address 08h)
7
6
5
4
3
N0.7
N0.6
N0.5
N0.4
N0.3
0
0
0
0
0
2
N0.2
0
1
N0.1
0
0
N0.0
0
Table 14.
Bit
Symbol
Default
Polarity inversion port 1 register (address 09h)
7
6
5
4
3
N1.7
N1.6
N1.5
N1.4
N1.3
0
0
0
0
0
2
N1.2
0
1
N1.1
0
0
N1.0
0
Table 15.
Bit
Symbol
Default
Polarity inversion port 2 register (address 0Ah)
7
6
5
4
3
N2.7
N2.6
N2.5
N2.4
N2.3
0
0
0
0
0
2
N2.2
0
1
N2.1
0
0
N2.0
0
6.5.4 Configuration registers (0Ch, 0Dh, 0Eh)
The Configuration registers (registers 0Ch, 0Dh, 0Eh) configure the direction of the I/O
pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register group write is described in Section 7.1 and a register
group read is described in Section 7.2.
Table 16.
Bit
Symbol
Default
Configuration port 0 register (address 0Ch)
7
6
5
4
3
C0.7
C0.6
C0.5
C0.4
C0.3
1
1
1
1
1
2
C0.2
1
1
C0.1
1
0
C0.0
1
Table 17.
Bit
Symbol
Default
Configuration port 1 register (address 0Dh)
7
6
5
4
3
C1.7
C1.6
C1.5
C1.4
C1.3
1
1
1
1
1
2
C1.2
1
1
C1.1
1
0
C1.0
1
PCAL6524
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 21 September 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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