PHP101NQ03LT Datasheet, PDF (3/13 Pages) NXP Semiconductors – TrenchMOS logic level FET

NXP Semiconductors
PHP101NQ03LT
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
V_DS
V_DGR
V_GS
I_D
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T_j ≥ 25 °C; T_j ≤ 175 °C
T_j ≥ 25 °C; T_j ≤ 175 °C; R_GS = 20 kΩ
V_GS = 10 V; T_mb = 100 °C; see Figure 1
V_GS = 10 V; T_mb = 25 °C; see Figure 1;
see Figure 3
I_DM
peak drain current
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
V_GSM
peak gate-source voltage
Source-drain diode
t_p ≤ 10 µs; pulsed; T_mb = 25 °C; see Figure 3
T_mb = 25 °C; see Figure 2
pulsed; δ = 25 %; t_p ≤ 50 µs; T_j ≤ 150 °C
I_S
source current
I_SM
peak source current
Avalanche ruggedness
T_mb = 25 °C
t_p ≤ 10 µs; pulsed; T_mb = 25 °C
E_DS(AL)S
non-repetitive
drain-source avalanche
energy
V_GS = 10 V; T_j(init) = 25 °C; I_D = 43 A;
V_sup ≤ 15 V; unclamped; t_p = 0.19 ms;
R_GS = 50 Ω
120
I_der
(%)
80
03ai19
120
P_der
(%)
80
Min Max Unit
-
30
V
-
30
V
-20 20
V
-
75
A
-
75
A
-
240 A
-
166 W
-55 175 °C
-55 175 °C
-25 25
V
-
75
A
-
240 A
-
185 mJ
03aa16
40
40
0
0
50
100
150
200
T_mb (°C)
0
0
50
100
150
200
T_mb (°C)
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PHP101NQ03LT_4
Product data sheet
Rev. 04 — 2 March 2009
© NXP B.V. 2009. All rights reserved.
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