ADC1115S125 Datasheet, PDF (3/35 Pages) NXP Semiconductors – Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 Pinning
terminal 1
index area
REFB 1
REFT 2
AGND 3
VCM 4
VDDA5V 5
AGND 6
INM 7
INP 8
AGND 9
VDDA3V 10
ADC1115S
HVQFN40
30 n.c.
29 n.c.
28 n.c.
27 D0
26 D1
25 D2
24 D3
23 D4
22 D5
21 D6
Transparent top view
005aaa147
Fig 2. Pin configuration with CMOS digital outputs
selected
terminal 1
index area
REFB 1
REFT 2
AGND 3
VCM 4
VDDA5V 5
AGND 6
INM 7
INP 8
AGND 9
VDDA3V 10
ADC1115S
HVQFN40
30 n.c.
29 n.c.
28 LOW_D0_P
27 LOW_D0_M
26 D1_D2_P
25 D1_D2_M
24 D3_D4_P
23 D3_D4_M
22 D5_D6_P
21 D5_D6_M
005aaa148
Transparent top view
Fig 3. Pin configuration with LVDS/DDR digital
outputs selected
6.2 Pin description
Table 2.
Symbol
REFB
REFT
AGND
VCM
VDDA5V
AGND
INM
INP
AGND
VDDA3V
VDDA3V
CLKP
CLKM
DEC
OE
PWD
Pin description (CMOS digital outputs)
Pin
Type ^[1]
Description
1
O
bottom reference
2
O
top reference
3
G
analog ground
4
O
common-mode output voltage
5
P
analog power supply 5 V
6
G
analog ground
7
I
complementary analog input
8
I
analog input
9
G
analog ground
10
P
analog power supply 3 V
11
P
analog power supply 3 V
12
I
clock input
13
I
complementary clock input
14
O
regulator decoupling node
15
I
output enable, active LOW
16
I
power down, active HIGH
ADC1115S125_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 April 2010
© NXP B.V. 2010. All rights reserved.
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